module power_pwm(
    input   wire         I_rst_n         ,
    
    input   wire         I_vs            ,
        
    input   wire         pwm_en          ,
    
    output  wire [7:0]  O_read_pwm_data  ,
    output  wire        O_power_en       ,
    output  wire        O_reset_en       ,
        
    input   wire         BL_clk          ,
    input   wire         BL_we           ,
    input   wire [12:0]  BL_waddr        ,
    input   wire [15:0]  BL_wdata        ,
    input   wire         BL_we_end       ,
        
    output  reg          BL_we_O          ,
    output  reg  [12:0]  BL_waddr_O       ,
    output  reg  [15:0]  BL_wdata_O       ,
    output  reg          BL_we_end_O      ,
    
    //设置总线          
    input   wire         set_clk     ,
    input   wire         set_d_ok    ,
    input   wire  [23:0] set_addr    ,
    input   wire  [7:0]  set_data
    
);

(* ASYNC_REG = "true" *)reg [5:0]vs;

always@(posedge BL_clk or negedge I_rst_n)
    if( !I_rst_n    )
        vs[0] <= 'b0;
    else
        vs[0] <= I_vs;

always@(posedge BL_clk or negedge I_rst_n)
    if( !I_rst_n    )
        vs[5:1] <= 4'b0;
    else
        vs[5:1] <= vs[4:0];


// 使用SPI 口发过来的占空比确定背光亮度
(* ASYNC_REG = "true" ,MARK_DEBUG="true" *)reg     [7:0]   read_pwm_data;
(* ASYNC_REG = "true" ,MARK_DEBUG="true" *)reg     [7:0]   read_pwm_data_delay;
(* ASYNC_REG = "true" ,MARK_DEBUG="true" *)reg             power_en    ;
(* ASYNC_REG = "true",MARK_DEBUG="true" *)reg             reset_en    ;
reg     [23:0]  pwm_data    ;

always@(posedge set_clk or negedge I_rst_n)
    if( !I_rst_n    )begin
        power_en <= 'd0;
        read_pwm_data <= 'd16;
        reset_en <= 'd0;
    end
    else if  (set_d_ok == 1)
       case (set_addr[23:0])
            24'hffff00: power_en        <= set_data[0]  ;
            24'hffff01: read_pwm_data   <= set_data     ;
            24'hffff02: reset_en        <= set_data[0]  ;
       endcase

assign O_read_pwm_data  = read_pwm_data_delay ;
assign O_power_en       = power_en      ;
assign O_reset_en       = reset_en      ;
/*
ila_spi_pwm_det  ila_spi_pwm_inst(
    .clk            (set_clk        ),
    .probe0         (set_d_ok       ),
    .probe1         (set_data       ),
    .probe2         (set_addr       ),
    .probe3         (read_pwm_data  ),
    .probe4         (power_en       )
);
*/
always @(posedge BL_clk or negedge I_rst_n)begin
    if(!I_rst_n)
        read_pwm_data_delay <= 'd100;
    else if(vs[5:4] == 2'b01)begin
        if( read_pwm_data < 'd32 )
            read_pwm_data_delay <= 'd32;
        else
            read_pwm_data_delay <= read_pwm_data;
        
     end
end

always @(posedge BL_clk)begin
    BL_we_O       <= BL_we ;
    BL_waddr_O    <= BL_waddr ;
    BL_we_end_O   <= BL_we_end ;
end


always @(posedge BL_clk)begin
    if( pwm_en  )
        pwm_data    <= BL_wdata * {1'b0,read_pwm_data_delay[7:0] };
    else
        pwm_data    <= BL_wdata * 9'h100;
end

always @(*)begin
    BL_wdata_O    <= pwm_data[23:8];
end

endmodule